MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 207

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.4 PWM SMx Control Register (PWM_SMnCTRL)
Addresses: PWM_SM0CTRL – F300h base + 3h offset = F303h
Freescale Semiconductor
Reset
Read
Write
Bit
CLK_SEL
15–12
LDFQ
HALF
Field
Field
1–0
11
15
0
PWM_SM1CTRL – F300h base + 33h offset = F333h
PWM_SM2CTRL – F300h base + 63h offset = F363h
14
0
LDFQ
Clock Source Select
These read/write bits determine the source of the clock signal for this submodule.
00
01
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Half Cycle Reload
This read/write bit enables half-cycle reloads. A half cycle is defined by when the submodule counter
matches the VAL0 register and does not have to be half way through the PWM cycle.
The IPBus clock is used as the clock for the local prescaler and counter.
EXT_CLK is used as the clock for the local prescaler and counter.
Submodule 0’s clock (AUX_CLK) is used as the source clock for the local prescaler and counter.
This setting should not be used in submodule 0 as it will force the clock to logic 0.
reserved
13
0
Every PWM Opportunity
Every 2 PWM Opportunities
Every 3 PWM Opportunities
Every 4 PWM Opportunities
Every 5 PWM Opportunities
Every 6 PWM Opportunities
Every 7 PWM Opportunities
Every 8 PWM Opportunities
Every 9 PWM Opportunities
Every 10 PWM Opportunities
Every 11 PWM Opportunities
Every 12 PWM Opportunities
Every 13 PWM Opportunities
Every 14 PWM Opportunities
Every 15 PWM Opportunities
Every 16 PWM Opportunities
PWM_SMnCTRL2 field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
HALF FULL
PWM_SMnCTRL field descriptions
11
0
Table continues on the next page...
10
1
0
9
Preliminary
DT
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
0
8
Description
Description
0
0
7
0
6
PRSC
0
5
0
4
0
0
3
0
2
0
0
1
0
0
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