MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 435

DSC 64K FLASH 60MHZ 64-LQFP

MC56F8257MLH

Manufacturer Part Number
MC56F8257MLH
Description
DSC 64K FLASH 60MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8257MLH

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
54
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Freescale Semiconductor
RSTAT
TSTAT
CSCIF
OVRIF
Field
RXF
5–4
3–2
6
1
0
0
1
CAN Status Change Interrupt Flag
This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the
transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0],
TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the
actual CAN bus status. If not masked, an error interrupt is pending while this flag is set. CSCIF provides a
blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only
updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value
after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits,
these bits keep their status until the current CSCIF interrupt is cleared again.
0
1
Receiver Status Bits
The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status
change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of
the MSCAN.
Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx
error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the
transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT coding in
this register.
00
01
10
11
Transmitter Status Bits
The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status
change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status
of the MSCAN.
00
01
10
11
Overrun Interrupt Flag
This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while
this flag is set.
0
1
Receive Buffer Full Flag
RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates
whether the shifted buffer is loaded with a correctly received message (matching identifier, matching
cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from
the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
No wakeup activity observed while in sleep mode
MSCAN detected activity on the CAN bus and requested wakeup
No change in CAN bus status occurred since last interrupt
MSCAN changed current CAN bus status
No data overrun condition
A data overrun detected
RxOK: 0 ≤ transmit error counter ≤ 96
RxWRN: 96 < transmit error counter ≤ 127
RxERR: 127 < transmit error counter ≤ 255
Bus-Off: transmit error counter > 255
TxOK: 0 ≤ transmit error counter ≤ 96
TxWRN: 96 < transmit error counter ≤ 127
TxERR: 127 < transmit error counter ≤ 255
Bus-Off: transmit error counter > 255
CAN_RFLG field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table continues on the next page...
Chapter 13 Freescale's Scalable Controller Area Network (MSCAN)
Preliminary
Description
435

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