MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 414

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Operating Modes
In a slave SPI (SPMSTR = 0), the MODF bit generates an SPI receiver/error DSC
interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset
the SPI in any way. Software can abort the SPI transaction by clearing the SPE bit of the
slave.
To clear the MODF flag, write a one to the MODF bit in the SCTRL register. The
clearing mechanism must occur with no MODF condition existing or else the flag is not
cleared.
12.4.5 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable
bit (SPE) is low. Whenever SPE is low, the following occurs:
Items 4 and 5 occur after 2 in slave mode, or after 3 in master mode.
The following items are reset only by a system reset:
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1. The SPTE flag is set
2. Any slave mode transaction currently in progress is aborted
3. Any master mode transaction currently in progress is continued to completion
4. The SPI state counter is cleared, making it ready for a new complete transaction
5. All the SPI port logic is disabled.
• The DXMIT and DRCV registers
A logic one voltage on the SS pin of a slave SPI puts the MISO
pin in a high impedance state. Also, the slave SPI ignores all
incoming SCLK clocks, even if it was already in the middle of
a transaction. A mode fault occurs if the SS pin changes state
during a transaction.
In a slave SPI, if the MODF flag is not cleared by writing a one
to the MODF bit, the condition causing the mode fault still
exists. In this case, the interrupt caused by the MODF flag can
be cleared by disabling the ERRIE or MODFEN bits (if set) or
by disabling the SPI. Disabling the SPI using the SPE bit causes
a partial reset of the SPI and may cause the loss of a message
currently being received or transmitted.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Freescale Semiconductor