MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 108

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
3.6 Functional Description
The high-speed comparator can be used to compare two analog input voltages applied to
Pn and Mn. The analog comparator output (ACO) is high when the non-inverting input is
greater than the inverting input, and is low when the non-inverting input is less than the
inverting input. This signal can be selectively inverted by setting the CR1[INV] bit to 1.
The SCR[IER] and SCR[IEF] bits select the condition that causes the comparator module
to assert an interrupt to the processor. The SCR[CFR] bit is set on a rising edge of the
comparator output. The SCR[CFF] bit is set on a falling edge of the comparator output.
The (optionally filtered) comparator output can be read directly through the SCR[COUT]
bit.
3.6.1 HSCMP Functional Modes
There are three main sub-blocks to the comparator module: the comparator itself, the
window function, and the filter function. The filter can be clocked from an internally
generated clock or from an external sample input. Additionally, the filter is
programmable with respect to how many samples must agree before a change on the
output is registered. In the simplest case, only one sample must agree, and the filter acts
as a simple sampler.
The external sample input is enabled using the CR1[SE] bit. When this bit is set, the
output of the comparator is sampled only on rising edges of the sample input.
108
COUT
Field
CFF
1
0
Analog Comparator Flag Falling
During normal operation, the CFF bit is set when a falling edge on COUT has been detected. The CFF bit
is cleared by writing a logic one to the bit. During STOP mode, CFF can be programmed as either edge or
level sensitive via the SMELB bit.
NOTE: Edge detection during STOP is only supported on platforms which allow peripherals to be
0
1
Analog Comparator Output
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.
A Falling edge on COUT has not been detected.
Falling edge on COUT has occurred.
clocked during STOP modes. If the CFF and CFR flags are to be active during STOP, then
SMELB must be set to “0” for cases where the it is not receiving a clock during STOP.
CMPx_SCR field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Description
Freescale Semiconductor