MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 181

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timing
This figure contains the timing for using the compare preload feature. The compare
preload cycle begins with a compare event on COMP2 causing CSCTRL[TCF2] to be
asserted. COMP1 is loaded with the value in the CMPLD1 (c3) one IP bus clock later. In
addition an interrupt is asserted by the timer and the interrupt service routine is executed
during which both comparator load registers are updated with new values (c4 and c5).
When CSCTRL[TCF1] is asserted, COMP2 is loaded with the value in CMPLD2 (c4).
And on the subsequent CSCTRL[TCF2] event, COMP1 is loaded with the value in
CMPLD1 (c5). The cycle starts over again as an interrupt is asserted and the interrupt
service routine clears CSCTRL[TCF1] and CSCTRL[TCF2] and calculates new values
for CMPLD1 and CMPLD2.
Freescale Semiconductor
CMPLD2[15:0]
CMPLD1[15:0]
COMP2[15:0]
COMP1[15:0]
counter[15:0]
Step 1--
Step 2--
Step 3--
Step 4--
Step 5--
OFLAG
IP clk
TCF2
TCF1
The counter continues counting until CNTR matches COMP2.
The interrupt service routine clears CSCTRL[TCF1] and CSCTRL[TCF2] and the ISR
loads CMPLD1 and CMPLD2 with the values for the next cycle. The counter
continues counting until CNTR matches COMP1.
One clock later, OFLAG toggles, CMPLD1 is copied to COMP1, LOAD is copied to
CNTR, the counter starts counting.
CNTR matches COMP2 value. CSCTRL[TCF2] is asserted and an interrupt request is
generated.
CSCTRL[TCF1] is asserted. One clock later, OFLAG toggles, CMPLD2 is copied to
COMP2, LOAD is copied to CNTR and the counter starts counting.
c2-1
c1
Step 1
c2
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
c2
c3
Figure 6-124. Compare Load Timing
0
Step 2
c2
1
c3-n
Preliminary
Step 3
Compare Preload Cycle
c3-1
Step 4
c3
c3
0
c4
c5
1
Step 5
Chapter 6 Quad Timer (TMR)
c4-1
c4
c4
c5
0
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