MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 157

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
LENGTH
ONCE
Field
SCS
DIR
8–7
6
5
4
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Secondary Count Source
These bits identify the external input pin to be used as a count command or timer command. The selected
input can trigger the timer to capture the current value of CNTR . The selected input can also be used to
specify the count direction. The selected signal can also be used as a fault input when CSCTRL[FAULT]
is set. The polarity of the signal can be inverted by SCTRL[IPS].
00
01
10
11
Count Once
This bit selects continuous or one shot counting mode.
0
1
Count Length
This bit determines whether the counter:
0
1
Count Direction
• counts to the compare value and then re-initializes itself to the value specified in the LOAD (or
• continues counting past the compare value to the binary roll over.
Count repeatedly.
Count until compare and then stop. If counting up, a successful compare occurs when the counter
reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a
COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1
value, continues to count to the COMP2 value, and then stops.
Roll over.
Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a
COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to
generate successful comparisons. For example, the counter counts until a COMP1 value is reached,
re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is
reached, and so on.
Counter 0 input pin
Counter 1 input pin
Counter 2 input pin
Counter 3 input pin
CMPLD2) register, or
Counter 2 input pin
Counter 3 input pin
Counter 0 output
Counter 1 output
Counter 2 output
Counter 3 output
IP bus clock divide by 1 prescaler
IP bus clock divide by 2 prescaler
IP bus clock divide by 4 prescaler
IP bus clock divide by 8 prescaler
IP bus clock divide by 16 prescaler
IP bus clock divide by 32 prescaler
IP bus clock divide by 64 prescaler
IP bus clock divide by 128 prescaler
TMRx_CTRL field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table continues on the next page...
Preliminary
Description
Chapter 6 Quad Timer (TMR)
157