MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 186

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Description of Interrupt Operation
6.9.2
6.9.2.1 Timer Compare Interrupts
These interrupts are generated when a successful compare occurs between a counter and
it's compare registers while SCTRL[TCFIE] is set. These interrupts are cleared by writing
a zero to the appropriate SCTRL[TCF].
When a timer compare interrupt is set in TMR_SCTRL and the Compare Load registers
are available, one of the following two interrupts will also be asserted.
6.9.2.1.1 Timer Compare 1 Interrupts (Available with Compare Load
These interrupts are generated when a successful compare occurs between a counter and
its COMP1 register while CSCTRL[TCF1EN] is set. These interrupts are cleared by
writing a zero to the appropriate CSCTRL[TCF1].
6.9.2.1.2 Timer Compare 2 Interrupts (Available with Compare Load
These interrupts are generated when a successful compare occurs between a counter and
its COMP2 register while CSCTRL[TCF2EN] is set. These interrupts are cleared by
writing a zero to the appropriate CSCTRL[TCF2].
6.9.2.2 Timer Overflow Interrupts
These interrupts are generated when a counter rolls over its maximum value while
SCTRL[TOFIE] is set. These interrupts are cleared by writing zero to the appropriate
SCTRL[TOF].
186
TMR Channel 3
Core Interrupt
Description of Interrupt Operation
Feature)
Feature)
TMR3_COMP1_IRQ_B Compare 1 Interrupt Request for Timer Channel 3
TMR3_COMP2_IRQ_B Compare 2 Interrupt Request for Timer Channel 3
TMR3_COMP_IRQ_B Compare Interrupt Request for Timer Channel 3
TMR3_EDGE_IRQ_B
TMR3_OVF_IRQ_B
Table 6-128. Interrupt Summary (continued)
Interrupt
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Overflow Interrupt Request for Timer Channel 3
Input Edge Interrupt Request for Timer Channel 3
Description
Preliminary
Freescale Semiconductor