MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 593

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

After all data is fed into CRC, the CRCH:CRCL result is available in the MSb format.
Then, these two bytes should also be transposed: the values read from CRCH:CRCL
should be written/read to/from the TRANSPOSE register.
Although the transpose feature was initially designed to address LSb applications
interfacing with the CRC module, it is important to notice that this feature is not
necessarily tied to CRC applications. Since it was designed as an independent register,
any application should be able to transpose data by writing/reading to/from the
TRANSPOSE register (e.g.: Big endian / Little endian conversion in USB).
19.5 Initialization Information
To initialize the CRC Module and initiate a CRC16-CCITT calculation, follow this
procedure:
Freescale Semiconductor
2. Read data from TRANSPOSE register (subsequent reads will result in the transposed
3. Write transposed byte to CRCL.
1. Write high byte of initial seed value to CRCH.
2. Write low byte of initial seed value to CRCL.
3. Write first byte of data on which CRC is to be calculated to CRCL.
4. In the next bus cycle after step 3, if desired, the CRC result from the first byte can be
5. Repeat steps 3-4 until the end of all data to be checked.
value of the last written data)
read from CRCH:CRCL.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Chapter 19 Cyclic Redundancy Check Generator (CRC)
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