MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 254

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
7.3.57 Master Control Register (PWM_MCTRL)
Address: PWM_MCTRL – F300h base + C4h offset = F3C4h
254
Reset
Read
Write
SM0SEL23
SM0SEL45
Bit
15–12
IPOL
11–8
RUN
Field
Field
3–2
1–0
15
0
14
0
10
11
Submodule 0 PWM23 Control Select
This field selects possible over-rides to the generated SM0PWM23 signal that will be passed to the
deadtime logic upon the occurrence of a FORCE_OUT event in that submodule.
00
01
10
11
Submodule 0 PWM45 Control Select
This field selects possible over-rides to the generated SM0PWM45 signal that will be passed to the
deadtime logic upon the occurrence of a FORCE_OUT event in that submodule.
00
01
10
11
IPOL
Current Polarity
This buffered read/write bit is used to select between PWM23 and PWM45 as the source for the
generation of the complementary PWM pair output. MCTRL[IPOL] is ignored in independent mode.
MCTRL[IPOL] does not take effect until a FORCE_OUT event takes place in the appropriate submodule.
Reading MCTRL[IPOL] reads the buffered value and not necessarily the value currently in effect.
0
1
Run
This read/write bit enables the clocks to the PWM generator. When this bit equals zero, the submodule
counter is reset. A reset clears this field.
PWM23 is used to generate complementary PWM pair.
PWM45 is used to generate complementary PWM pair.
SWCOUT[SM1OUT45] is used by the deadtime logic.
PWM1_EXTB signal is used by the deadtime logic.
Generated SM0PWM23 signal is used by the deadtime logic.
Inverted generated SM0PWM23 signal is used by the deadtime logic.
SWCOUT[SM0OUT23] is used by the deadtime logic.
PWM0_EXTA signal is used by the deadtime logic.
Generated SM0PWM45 signal is used by the deadtime logic.
Inverted generated SM0PWM45 signal is used by the deadtime logic.
SWCOUT[SM0OUT45] is used by the deadtime logic.
PWM0_EXTB signal is used by the deadtime logic.
13
0
PWM_DTSRCSEL field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
PWM_MCTRL field descriptions
Table continues on the next page...
10
0
RUN
0
9
Preliminary
0
8
Description
Description
0
7
0
6
CLDOK
0
5
0
4
0
3
Freescale Semiconductor
0
2
LDOK
0
1
1
0