MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 415

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

By not resetting the control bits when SPE is low, the user can clear SPE between
transactions without having to set all control bits again when SPE is set back high for the
next transaction.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these
interrupts after the SPI is disabled. The user can disable the SPI by writing 0 to the SPE
bit. The SPI is also disabled when a mode fault occurs in an SPI configured as a master.
12.5 Interrupts
Four SPI status flags can be enabled to generate DSC interrupt requests.
Freescale Semiconductor
(Transmitter Empty)
• All control bits in the SCTRL register (MODFEN, ERRIE, SPR2, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
(Receiver Full)
(Mode Fault)
(Overflow)
MODF
OVRF
SPTE
SPRF
Flag
SPI EnableSPI Transmitter Interrupt
SPI Receiver/Error Interrupt Enable
SPI Receiver/Error Interrupt Ena‐
MODF Enable(ERRIE = 1, MOD‐
Enable(SPTIE = 1, SPE = 1)
SPI Receiver Interrupt Ena‐
ble(SPRIE = 1, SPE = 1)
Interrupt Enabled By
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
ble(ERRIE = 1)
FEN=1)
Table 12-11. SPI Interrupts
Preliminary
The SPI transmitter interrupt enable bit (SPTIE) enables the
SPI transmitter empty (SPTE) flag or TFWM to generate
transmitter interrupt requests, provided that the SPI is ena‐
bled (SPE = 1). The SPTE bit becomes set every time data
transfers from the transmit data register (DXMIT) to the shift
register and there is no more new data available in the Tx
queue. The clearing mechanism for the SPTE flag is a write
to the DXMIT register.
The SPI receiver interrupt enable bit (SPRIE) enables the
SPI receiver full (SPRF) bit or RFWM to generate receiver in‐
terrupt requests. The SPRF is set every time data transfers
from the shift register to the receive data register (DRCV) and
there is no more room available in the RX queue to receive
new data. The clearing mechanism for the SPRF flag is to
read the DRCV register.
The error interrupt enable bit (ERRIE) enables both the
MODF and OVRF bits to generate a receiver/error interrupt
request.
The mode fault enable bit (MODEFEN) enables the mode
fault (MODF) bit to generate the receiver/error interrupt re‐
quest regardless of the state of the SPE bit. The mode fault
enable bit (MODFEN) can prevent the MODF flag from being
set, so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error DSC interrupt requests.
Description
Chapter 12 Queued Serial Peripheral Interface (QSPI)
415