MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 230

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
7.3.28 PWM SM3 Value Register 0 (PWM_SM3VAL0)
Address: PWM_SM3VAL0 – F300h base + 95h offset = F395h
7.3.29 PWM SM3 Value Register 1 (PWM_SM3VAL1)
Address: PWM_SM3VAL1 – F300h base + 97h offset = F397h
230
Reset
Reset
Read
Read
Write
Write
Bit
Bit
VAL0
VAL1
15–0
15–0
Field
Field
15
15
0
0
14
14
0
0
Value Register 0
The 16-bit signed value in this buffered, read/write register defines the mid-cycle reload point for the PWM
in PWM clock periods. This value also defines when the PWMX signal is set and the local sync signal is
reset. This register is not byte accessible.
NOTE: The VAL0 register is buffered. The value written does not take effect until MCTRL[LDOK] is set
Value Register 1
The 16-bit signed value written to this buffered, read/write register defines the modulo count value
(maximum count) for the submodule counter. Upon reaching this count value, the counter reloads itself
with the contents of the INIT register and asserts the local sync signal while resetting PWMX. This register
is not byte accessible.
NOTE: The VAL1 register is buffered. The value written does not take effect until MCTRL[LDOK] is set
13
13
0
0
and the next PWM load cycle begins or CTRL[LDMOD] is set. VAL0 cannot be written when
MCTRL[LDOK] is set. Reading VAL0 reads the value in a buffer. It is not necessarily the value
the PWM generator is currently using.
and the next PWM load cycle begins or CTRL[LDMOD] is set. VAL1 cannot be written when
MCTRL[LDOK] is set. Reading VAL1 reads the value in a buffer. It is not necessarily the value
the PWM generator is currently using.
12
12
0
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SM3VAL0 field descriptions
PWM_SM3VAL1 field descriptions
11
11
0
0
10
10
0
0
0
0
9
9
Preliminary
0
0
8
8
VAL0
VAL1
Description
Description
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
0
0
3
3
Freescale Semiconductor
0
0
2
2
0
0
1
1
0
0
0
0