MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 406

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Operating Modes
Figure 12-12. Transaction Format (CPHA = 1)
Two waveforms are shown for SCLK: one for CPOL = 0 and another for CPOL = 1. The
diagram may be interpreted as a master or slave timing diagram since the serial clock
(SCLK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the output from the
slave, and the MOSI signal is the output from the master.
When CPHA = 1 for a slave, the first edge of the SCLK indicates the beginning of the
transaction. This causes the SPI to leave its idle state and begin driving the MISO pin
with the first bit of its data. After the transaction begins, no new data is allowed into the
shift register from the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SCLK. Any data written after
the first edge is stored in the transmit data register and transferred to the shift register
after the current transaction. The SS line is the slave select input to the slave. The slave
SPI drives its MISO output only when its slave select input (SS) is at logic zero, so that
only the selected slave drives to the master.
When CPHA = 1 for a master, the MOSI pin begins being driven with new data on the
first SCLK edge. If MODFEN = 0 the SS pin of the master is ignored. Otherwise, the SS
pin of the master must be high or a mode fault error occurs. The SS pin can remain low
between transactions. This format may be preferable in systems with only one master and
one slave driving the MISO data line.
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MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
406
Freescale Semiconductor