MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 469

DSC 64K FLASH 60MHZ 64-LQFP

MC56F8257MLH

Manufacturer Part Number
MC56F8257MLH
Description
DSC 64K FLASH 60MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8257MLH

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
54
Data Ram Size
8 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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13.4.3.1 Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through
programming errors. The protection logic implements the following features:
>
13.4.3.2 Clock System
This figure shows the structure of the MSCAN clock generation circuitry.
Freescale Semiconductor
• The receive and transmit error counters cannot be written or otherwise manipulated.
• All registers that control the configuration of the MSCAN cannot be modified while
• The TXCAN pin is immediately forced to a recessive state when the MSCAN goes
• The MSCAN enable bit (CANE) is writable only once in normal system operation
the MSCAN is on-line. The MSCAN must be in initialization mode. The
corresponding INITRQ/INITAK handshake bits in the CAN_CTL0/CAN_CTL1
registers serve as a lock to protect the following registers:
into the power down mode or initialization mode.
modes, which provides further protection against inadvertently disabling the
MSCAN.
• MSCAN control 1 register (CAN_CTL1)
• MSCAN bus timing registers 0 and 1 (CAN_BTR0, CAN_BTR1)
• MSCAN identifier acceptance control register (CAN_IDAC)
• MSCAN identifier acceptance registers (CAN_IDAR0–CAN_IDAR7)
• MSCAN identifier mask registers (CANIDMR0–CANIDMR7)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Chapter 13 Freescale's Scalable Controller Area Network (MSCAN)
Preliminary
469

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