MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 50

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
2.3.2 ADC Control Register 2 (ADC_CTRL2)
Address: ADC_CTRL2 – F080h base + 1h offset = F081h
50
Reset
Read
Write
Bit
Reserved
START1
STOP1
Field
Field
15
14
13
15
0
0
14
1
100
101
11x
This read-only bit is reserved and always has the value zero.
Stop
During parallel scan modes when SIMULT = 0, this bit enables stop control of a B converter parallel scan.
When this bit is asserted, the current scan is stopped and no further scans can start. Any further SYNC1
input pulses (see CTRL2[SYNC1] bit) or writes to the CTRL2[START1] bit are ignored until this bit has
been cleared. After the ADC is in stop mode, the results registers can be modified by the processor. Any
changes to the result registers in stop mode are treated as if the analog core supplied the data. Therefore,
limit checking, zero crossing, and associated interrupts can occur when authorized. This is not the same
as DSP STOP mode.
0
1
START1 Conversion
START
Normal operation
Stop mode
13
0
1
0
0, a converter restarts scanning when it encounters a disabled sample. If PWR[ASB] or PWR[APD]
is the selected power mode control, PWR[PUDELAY] is applied only on the first conversion.
Triggered sequential — Upon start or an enabled sync signal, samples are taken one at a time
starting with CLIST1[SAMPLE0], until the first disabled sample is encountered. If no disabled
sample is encountered, conversion concludes after CLIST4[SAMPLE15]. If external sync is
enabled, new scans start for each SYNC pulse that does not overlap with a current scan in
progress.
Triggered parallel (default) — Upon start or an enabled sync signal: In parallel, converter A
converts SAMPLEs 0-3, 8-11, and converter B converts SAMPLEs 4-7, 12-15. When
CTRL2[SIMULT] is 1 (default), scanning stops when either converter encounters a disabled
sample. When CTRL2[SIMULT] is 0, a converter stops scanning when it encounters a disabled
sample. If external sync is enabled, new scans start for each SYNC pulse that does not overlap
with a current scan in progress.
Reserved
12
ADC_CTRL1 field descriptions (continued)
1
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
ADC_CTRL2 field descriptions
Table continues on the next page...
10
0
0
0
9
Preliminary
CHNCFG_H
0
8
Description
Description
0
7
0
6
1
5
0
4
0
3
Freescale Semiconductor
DIV
0
2
1
1
0
0