MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 413

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.4.4.2.1 Master Mode Fault
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag
(MODF) is set if SS goes to logic zero. A mode fault in a master SPI causes the following
events to occur:
In a master SPI, the MODF flag is not cleared until the SS pin is at a logic one or the SPI
is configured as a slave.
12.4.4.2.2 Slave Mode Fault
When configured as a slave (SPMSTR = 0), the MODF flag is set if the SS pin goes high
during a transaction. When CPHA = 0, a transaction begins when SS goes low and ends
after the incoming SCLK goes back to its idle level following the shift of the last data bit.
When CPHA = 1, the transaction begins when the SCLK leaves its idle level and SS is
already low. The transaction continues until the SCLK returns to its idle level following
the shift of the last data bit.
Freescale Semiconductor
• If ERRIE = 1, the SPI generates an SPI receiver/error DSC interrupt request.
• The SPE bit is cleared (SPI disabled).
• The SPTE bit is set.
• The SPI state counter is cleared.
Setting the MODF flag does not clear the SPMSTR bit. The
SPMSTR bit has no function when SPE = 0. Reading SPMSTR
when MODF = 1 shows the difference between a MODF
occurring when the SPI is a master and when it is a slave. When
CPHA = 0, a MODF occurs if a slave is selected (SS is at logic
zero) and later unselected (SS is at logic one) after the first bit
of data has been received (SCLK is toggled at least once). This
happens because SS at logic zero indicates the start of the
transaction (MISO driven out with the value of MSB) for
CPHA = 0. When CPHA = 1, a slave can be selected and then
later unselected with no transaction occurring. Therefore,
MODF does not occur since a transaction was never begun.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Chapter 12 Queued Serial Peripheral Interface (QSPI)
413