MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 563

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 16 System Integration Module (SIM)
16.3
Functional Description
16.3.1 Clock Generation Overview
The SIM uses master clocks from the OCCS module to produce the peripheral and
system (DSC core and memory) clocks. A mstr_2x clock input from OCCS operates at
two times the system and peripheral bus rate and therefore a maximum of 120 MHz.
Peripheral and system clocks are generated at a maximum of 60 MHz by dividing the
mstr_2x clock by 2 and gating it with appropriate power mode and clock gating controls.
The TMR and SCI peripheral clocks can optionally be generated at two times the normal
rate, at a maximum of 120 MHz. These clocks are generated by gating the mstr_2x clock
with appropriate power mode and clock gating controls.
The OCCS configuration controls the operating frequency of the SIM's master clocks. In
the OCCS, an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can
be selected as the master clock source (mstr_osc). An external clock can be operated at
any frequency up to 120 MHz. An external clock is presented directly to the SIM as the
mstr_2x clock, so the duty cycle of the high-speed peripheral clock would reflect the
precision of the duty cycle of the external clock. The crystal oscillator can be operated at
between 8 MHz and 16 MHz. The relaxation oscillator can be operated at full speed (8
MHz), standby speed (400 kHz using ROSB), or powered down (using ROPD). An 8
MHz or 16 MHz mstr_osc can be multiplied to 240 MHz using the PLL and postscaled to
provide a variety of speed clock rates. Either the postscaled PLL output or mstr_osc
signal can be selected to produce the master clocks to the SIM.
In combination with the OCCS module, the SIM provides power modes (see the
following section), clock enables (PCEn registers, SDn registers, CLKDIS, ONCEEBL),
and clock rate controls (TMRn_CR, SCIn_CR) to provide flexible control of clocking
and power use. The SIM's PCEn peripheral clock enable controls can be used to disable
individual peripheral clocks when they are not needed. The clock rate controls enable the
high speed clocking option for the general-purpose timers and the SCIs. See the OCCS
chapter for further details.
16.3.2 Power Down Modes Overview
The 56800E DSC core operates in the power modes shown in the following table.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor
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