MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 433

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.3.5 MSCAN Bus Timing Register 1 (CAN_BTR1)
The CAN_BTR1 register configures various CAN bus timing parameters of the MSCAN
module.
Address: CAN_BTR1 – F440h base + 3h offset = F443h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
TSEG2
TSEG1
SAMP
15–8
Field
6–4
3–0
7
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
Sampling
This bit determines the number of CAN bus samples taken per bit time.
0
1
Time Segment 2
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point.
000
001
010
011
100
101
110
111
Time Segment 1
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point.
0000
0001
0010
0011
0100
One sample per bit. The resulting bit value is equal to the value of the single bit positioned at the
sample point.
Three samples per bit. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). The resulting
bit value is determined by using majority rule on the three total samples. For higher bit rates, it is
recommended that only one sample is taken per bit time (SAMP=0)
13
0
1 Tq clock cycle (This setting is not valid)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
5 Tq clock cycles
6 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycles (This setting is not valid)
2 Tq clock cycles (This setting is not valid)
3 Tq clock cycles (This setting is not valid)
4 Tq clock cycles
5 Tq clock cycles
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
11
0
CAN_BTR1 field descriptions
Table continues on the next page...
10
0
Chapter 13 Freescale's Scalable Controller Area Network (MSCAN)
0
9
Preliminary
0
8
Description
0
7
0
6
TSEG2
0
5
0
4
0
3
0
2
TSEG1
0
1
0
0
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