MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 584

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
18.3.1 COP after Reset
CEN is set out of reset. Thus the counter is enabled by default. In addition, the TOUT
register is set to its maximum value of 0xFFFF and PRESCALER is set to 1024
(CTRL[PSS]=11) during reset so the counter is loaded with a maximum timeout period
when reset is released.
If the IP bus clock to the COP is not enabled by default after reset, then allow 2 clock
cycles to occur after enabling it before performing a write access to the COP.
18.3.2 Wait Mode Operation
If wait mode is entered with both CEN and CWEN set to 1, then the COP counter
continues to count down. In that case, a COP reset is issued to wake the device after the
counter reaches zero. If either CEN or CWEN is cleared to 0 when wait mode is entered,
then the counter is disabled and reloads using the value in the TOUT register.
18.3.3 Stop Mode Operation
If stop mode is entered with both CEN and CSEN set to 1, then the COP counter
continues to count down. In that case, a COP reset is issued to wake the device after the
counter reaches zero. If either CEN or CSEN is cleared to 0 when stop mode is entered,
then the counter is disabled and reloads using the value in the TOUT register.
18.3.4 Debug Mode Operation
The COP counter is not allowed to count when the device is in debug mode. In addition,
the CEN bit in the CTRL register always reads as zero when the device is in debug. The
actual value of CEN is unaffected by debug, however, and resumes its previously set
value upon exiting debug.
18.3.5 Loss of Reference Operation
When the OCCS signals the COP that a loss of the reference clock has occurred and the
CLOREN bit is set, then the COP starts a 7-bit counter that runs off of the IP bus clock
(which continues to be produced by the PLL for at least 1000 cycles upon losing its
reference). The counter continues to count once started counting. When this counter
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
584
Freescale Semiconductor