MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 311

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.2.6 GPIO Interrupt Enable Register (GPIOx_IENR)
This register enables or disables the edge interrupt from each GPIO pin. Set a bit to 1 to
enable the interrupt for the associated GPIO pin. The interrupt is recorded in the
corresponding GPIO Interrupt Pending register.
Addresses: GPIOA_IENR – F140h base + 5h offset = F145h
9.2.7 GPIO Interrupt Polarity Register (GPIOx_IPOLR)
This read/write register is used for polarity detection caused by any external interrupts.
The interrupt at the pin is active low when this register is set to one (falling edge causes
the interrupt). The interrupt seen at the pin is active high when this register is set to zero
(rising edge causes the interrupt).
Freescale Semiconductor
Reset
Read
Write
Bit
15–0
Field
Field
IEN
15
0
GPIOB_IENR – F150h base + 5h offset = F155h
GPIOC_IENR – F160h base + 5h offset = F165h
GPIOD_IENR – F170h base + 5h offset = F175h
GPIOE_IENR – F180h base + 5h offset = F185h
GPIOF_IENR – F190h base + 5h offset = F195h
14
0
0
1
Interrupt Enable Bits
0
1
Deassert software interrupt
Assert software interrupt
External Interrupt is disabled
External Interrupt is enabled
13
0
12
GPIOx_IAR field descriptions (continued)
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
GPIOx_IENR field descriptions
10
0
0
9
Preliminary
0
8
IEN
Description
Description
0
7
Chapter 9 General-Purpose Input/Output (GPIO)
0
6
0
5
0
4
0
3
0
2
0
1
0
0
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