MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 521

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.3 OCCS PLL Status Register (OCCS_STAT)
A PLL interrupt is generated if any of the LOLI or LOCI bits are set and the respective
interrupt enable is set in the CTRL.
Address: OCCS_STAT – F120h base + 2h offset = F122h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
PLLDB
LOLI1
Field
Field
6–0
15
7
15
0
14
0
0111
1xxx
This read-only bit is reserved and always has the value zero.
PLL Divide By
The output frequency of the PLL is controlled, in part, by the PLLDB[6:0] field. The value written to this
field, plus one, is used by the PLL to directly multiply the input frequency and present it at its output. For
example, if the input frequency is 8MHz and the PLLDB[6:0] field is set to 29 (the default), then the PLL
output frequency is 240MHz. This yields a 120MHz sys_clk_2x. Dividing this by 2 (hardcoded into the
SIM) results in a 60MHz system clock assuming that the postscaler is set to one.
Before changing the divide-by value, you must switch the core clock to the MSTR_OSC clock.
PLLDB settings should be limited such that the output frequency of the PLL does not exceed 240 MHz.
NOTE: Upon writing to the DIVBY register, the Loss of Reference detector circuit is reset.
PLL Loss of Lock Interrupt 1
LOLI1 shows the status of the lock detector state from LCK1 circuit. This bit is cleared by writing a one to
LOLI0.
This bit will not be set (by the hardware) if the corresponding CTRL PLLIE1 bit is cleared (set to zero).
0
1
LOCI
PLL locked
PLL not locked
13
0
Divide by 128
Divide by 256
OCCS_DIVBY field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
OCCS_STAT field descriptions
Table continues on the next page...
10
0
0
0
9
Preliminary
0
8
Description
Description
0
7
LCK1 LCK0
—
0
6
Chapter 15 On-Chip Clock Synthesis (OCCS)
—
0
5
—
1
4
RESERVED
0
3
0
0
2
0
1
ZSRCS
—
1
0
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