MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 35

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1.4 Peripheral Subsystem
All functional pins on this device are multiplexed with one of the GPIO ports. To use one
of the pins as a peripheral pin, enable the peripheral function by programming the
corresponding bit in the GPIO port's peripheral enable register. If a pin is multiplexed
with different peripheral functions, control the selection of the peripheral function by
using one of the GPIO peripheral select registers in the System Integration Module
(SIM).
Freescale Semiconductor
Program Control Unit
HWS0
HWS1
FIRA
Manipulation
LA2
LA
PC
JTAG TAP
EOnCE™
OMR
LC2
SR
LC
Unit
Bit-
FISR
Figure 1-1. DSP56800E Core Block Diagram
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Instruction
Interrupt
Decoder
Looping
DSP56800E Core
Unit
Unit
Y
C2
D2
A2
B2
MAC and ALU
Generation
Preliminary
Address
(AGU)
A1
B1
C1
Y1
Y0
X0
D1
Unit
M01
N3
Multi-Bit Shifter
Arithmetic
Logic Unit
(ALU)
Data
ALU1
A0
B0
C0
D0
R0
R1
R2
R3
R4
R5
N
SP
ALU2
CDBW
CDBR
XAB1
XAB2
XDB2
PAB
PDB
Chapter 1 Device Overview
Program
Interface
Interface
External
Memory
Memory
IP Bus
Data
Bus
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