TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 105
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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0xE000_ED18
0xE000_ED1C
0xE000_ED20
8.6.2.15 System Handler Priority Registers
exception.
bits for assigning a priority.
Fault and Usage Fault. The System Handler Priority Registers for all other exceptions have the identical
fields. Unused bits return “0” when read, and writing to unused bits has no effect.
Each exception is provided with eight bits of a System Handler Priority Register.
The following shows the addresses of the System Handler Priority Registers corresponding to each
The number of bits to be used for assigning a priority varies with each product. This product uses three
The following shows the fields of the System Handler Priority Registers for Memory Management, Bus
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
31
(SysTick)
(SVCall)
PRI_15
PRI_11
PRI_7
Priority of Memory Management
15
23
31
7
Priority of Usage Fault
Priority of Bus Fault
24
Reserved
PRI_4
PRI_5
PRI_6
PRI_7
23
R/W
R/W
R/W
R/W
14
22
30
6
0
0
0
0
Under development
(Usage Fault)
(PendSV)
PRI_10
PRI_14
PRI_6
13
21
29
Page93
5
16
12
20
28
4
15
(Bus Fault)
PRI_13
PRI_5
PRI_9
19
27
11
3
“0” is read.
“0” is read.
“0” is read.
“0” is read.
10
18
26
2
R
R
R
0
0
R
0
0
8
7
(Debug Monitor)
Management)
17
25
1
9
(Memory
PRI_12
PRI_4
PRI_8
TMPM330
16
24
0
8
0
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