TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 166
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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TBnCR
(0x4001_0xx8)
10 16-bit Timer/Event Counters (TMRBs)
<TBmWBF>:Controls the enabling/disabling of double buffering.
<I2TBm>:Controls the operation in the IDLE mode.
<TBnSYNC>:Controls operation mode of timers.
10.4.1.3 TMRB control register (channels 0 through 9)
Read/Write
Read/Write
Read/Write
bit Symbol
Read/Write
After reset
bit Symbol
After reset
bit Symbol
After reset
bit Symbol
After reset
Function
Double
Buffer
0:
Disabled
1: Enabled
7
TBnWBF
“0”: timers operate individually.
“1”: timers operate synchronously.
R/W
31
23
15
R
R
R
0
0
0
0
Write “0”.
6
R/W
30
22
14
R
R
R
0
0
0
0
TMRBn control register (n=0~9)
Timer
operation
mode
0:individual
1:synchron
ous
TBnSYNC
Under development
5
R/W
29
21
13
R
R
R
0
0
0
0
Page154
“0” is read. IDLE
4
28
20
12
R
R
R
R
0
0
0
0
0:Stop
1:Operatio
n
3
I2TBn
R/W
27
19
11
R
R
R
0
0
0
0
“0” is read.
2
26
18
10
R
R
R
0
0
0
1
25
17
R
R
9
R
R
0
0
0
0
0
24
16
R
R
8
R
0
0
0
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