TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 109

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

IMCGB
8.6.3.2
(Note 1)
(Note 2)
CG Interrupt Mode Control Register B
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
“0” is read. Active state setting of INT4 standby
“0” is read. Active state setting of INT5 standby
“0” is read. Active state setting of INTCECRX
“0” is read. Active state setting of INTRMCRX0
Refer to EMSTxx bit to know the active condition which is used for clearing
standby.
Please specify the bit for the edge first and then specify the bit for the
<INTxEN>. Setting them simultaneously is prohibited.
15
23
31
7
R
R
R
R
0
0
0
0
Set it as shown below.
Set it as shown below.
clear request. (101~111: setting
prohibited)
standby clear request.
standby clear request.
clear request (101~111: setting
prohibited)
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
000: “L” level
001: “H” level
010: Falling edge
011: Rising edge
100: Both edges
011: Rising edge
011: Rising edge
EMCG42
EMCG52
EMCG62
EMCG72
14
22
30
6
0
0
0
0
Under development
EMCG41
EMCG51
EMCG61
EMCG71
R/W
R/W
R/W
R/W
13
21
29
Page97
5
1
1
1
1
EMCG40
EMCG50
EMCG60
EMCG70
12
20
28
4
0
0
0
0
standby clear request
standby clear request
standby clear request
Active state of INT4
Active state of INT5
Active state of
INTCECRX
Active state of
INTRMCRX0 standby
clear request
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
00: －
01: Rising edge
10: Falling edge
11: Both edges
EMST41
EMST51
EMST61
EMST71
19
27
11
3
0
0
0
0
R
R
R
R
EMST40
EMST50
EMST60
EMST70
10
18
26
2
0
0
0
0
“0” is read. INT4 clear
“0” is read. INT5 clear
“0” is read. INTCEC
“0” is read. INTRMC
17
25
1
R
9
R
R
R
0
0
0
0
input
0: Disable
1: Enable
input
0: Disable
1: Enable
1: Enable
1: Enable
RX clear
input
0: Disable
RX0 clear
input
0: Disable
INT5EN
INT7EN
INT4EN
INT6EN
TMPM330
R/W
R/W
R/W
R/W
16
24
0
8
0
0
0
0