TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 265

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

SCL
SDA
<PIN>
INTS0
interrupt request
(Note) The user can only use a DMA transfer:
Fig. 12-14 Generation of the Start Condition and a Slave Address
Slave mode
In the slave mode, the SBI receives the start condition and a slave address.
After receiving the start condition from the master device, the SBI receives a slave
address and a direction bit from the master device during the first eight clocks on the
SCL line. If the received address matches its slave address specified at SBIxI2CAR
or is equal to the general-call address, the SBI pulls the SDA line to the “L” level during
the ninth clock and outputs an acknowledgment signal.
The INTSBIx interrupt request is generated on the falling of the ninth clock, and <PIN>
is cleared to “0.” In the slave mode, the SBI holds the SCL line at the “L” level while
<PIN> is “0”.
Start condition
• when there is only one master and only one slave and
• continuous transmission or reception is possible.
A6
1
A5
2
Under development
A4
3
Page253
Slave address + Direction bit
A3
4
A2
5
A1
6
A0
7
R/
W
8
Master output
Slave output
ACK
9
TMPM330
Acknowledgement
from slave