TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 259
TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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12.5.7
SCL line
SDA line
Start condition
Generating Start and Stop Conditions
When SBIxSR<BB> is “0,” writing “1” to SBIxCR2 <MST, TRX, BB, PIN> causes the SBI to
generate the start condition on the bus and output 8-bit data. <ACK> must be set to “1” in
advance.
a sequence for generating the stop condition on the bus. The contents of <MST, TRX, BB,
PIN> should not be altered until the stop condition appears on the bus.
SBIxSR<BB> can be read to check the bus state. <BB> is set to “1” when the start
condition is detected on the bus (the bus is busy), and set to “0” when the stop condition is
detected (the bus is free).
When <BB> is “1,” writing “1” to <MST, TRX, PIN> and “0” to <BB> causes the SBI to start
Fig. 12-10 Generating the Start Condition and a Slave Address
Fig. 12-11 Generating the Stop Condition
A6
SCL line
SDA line
1
A5
2
Under development
Page247
A4
Slave address and direction bit
3
A3
4
Stop condition
A2
5
A1
6
A0
7
R/W
8
Acknowledgement
signal
TMPM330
9
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