TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 305
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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(8)
(9)
address does not correspond with the address set in the logical address register.
However, an ACK response of neither the header block nor the data block is sent.
bit detection respectively.
start bit rising timing ((1) in the figure shown below).
maximum cycle of a start bit ((2) in the figure shown below).
bit is considered to be valid.
(Note)
By setting CECRCR1 <CECOTH>, you can specify if data is received or not when destination
In this case, data is received as usual, and an interrupt is generated by detecting an error.
Configuring the CECRCR2 register allows you to specify the rising timing and a cycle of the start
<CECSWAV0> is to specify the fastest start bit rising timing. <CECSWAV1> is to specify the latest
<CECSWAV2> is to specify the minimum cycle of a start bit. <CECSWAV3> is to specify the
If a rising edge during the period (1) and a falling edge during the period (2) are detected, the start
Data Reception at Logical Address Discrepancy
Start Bit Detection
A broadcast message is received regardless of the <CECOTH> register setting.
0ms
<CECSWAV0>
3.5ms-7cycle
3.5ms~
Under development
Page293
3.5ms
<CECSWAV1>
3.7ms~
3.7ms+7cycle
(1)
3.7ms
<CECSWAV2>
4.3ms-7cycle
4.3ms~
4.3ms
(2)
4.7ms
<CECSWAV3>
4.7ms~
4.7ms+7cycle
TMPM330
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