TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 245
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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12.2 Control
(address)
Register
•
•
•
•
•
•
•
name
Serial bus interface control registers 0 (SBIxCR0)
Serial bus interface control registers 1 (SBIxCR1)
Serial bus interface control registers 2 (SBIxCR2)
Serial bus interface buffer registers (SBIxDBR)
I
Serial bus interface status registers (SBIxSR)
The following registers control the serial bus interface and provide its status information for
monitoring.
Serial bus interface baud rate registers 0 (SBIxBR0)
The functions of these registers vary, depending on the mode in which the SBI is operating. For
a detailed description of the registers, refer to “12.5 Control in the I2C Bus Mode” and “0
Control in the Clock-synchronous 8-bit SIO Mode”.
The addresses of each register are shown below.
2
C bus address register (SBIxI2CAR)
I
2
C bus address register
baud rate register 0
Serial bus interface
Serial bus interface
Serial bus interface
Serial bus interface
Serial bus interface
Serial bus interface
data buffer register
control register 0
control register 1
control register 2
status register
SBI0CR0
SBI0CR1
SBI0CR2
(reading)
SBI0SR
(writing)
SBI0BR0
SBI0DBR
SBI0I2CAR 0x4002_000C
Channel 0
Under development
0x4002_0014
0x4002_0000
0x4002_0004
0x4002_0010
0x4002_0008
Page233
SBI1CR0
SBI1CR1
SBI1CR2
(reading)
SBI1SR
(writing)
SBI1BR0
SBI1DBR
SBI1I2CAR
Channel 1
0x4002_0020
0x4002_0024
0x4002_0034
0x4002_0030
0x4002_0028
0x4002_002C
SBI2CR0
SBI2CR1
SBI2CR2
(reading)
SBI2SR
(writing)
SBI2BR0
SBI2DBR
SBI2I2CAR
Channel 2
0x4002_0040
0x4002_0044
0x4002_0054
0x4002_0050
0x4002_0048
0x4002_004C
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