TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 370

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

16 Watchdog Timer (Runaway Detection Timer)
16.2 Watchdog Timer Interrupt
WDT counter
WDT interrupt
WDT clear
WDTOUT
The watchdog timer consists of the binary counters that are arranged in 26 stages and work using the
f
2
interrupt
Fig. 16-2.
The
identified with the NMIFLG <NMIFLG0> bit in the clock generator
The output pin of the watchdog timer can reset the peripherals by outputting “0” caused by an
overflow. The output is set to “1”if the watchdog timer is cleared (if the clear code 4EH is written to the
WDCR register). The
WDCR register.
(Note)
When an overflow occurs, resetting the chip itself is an option to choose. If the chip is reset, a reset is
affected for a 32-state time, as shown in Fig. 16-3. If this reset is affected, the clock f
gear generates by dividing the clock f
WDT counter
WDT interrupt
Internal reset
WDTOUT
SYS
22
, 2
system clock as an input clock. The outputs produced by these binary counters are 2
INTWDT
24
are 2
The TMPM330 does not include a watchdog timer out pin (
INTWDT
interrupt is one of the non-maskable interrupt factors. The
26
.By selecting one of these outputs with WDMOD <WDTP2:0>, a watchdog timer
can be generated and the
n
n
WDTOUT
Overflow
pin outputs “0” at normal mode unless the clear code is written to
(3.2 μs @ fosc = 10 MHz, f
Fig. 16-2 Normal Mode
Fig. 16-3 Reset Mode
Under development
C
of the high-speed oscillator by 1 is used as an input clock f
Overflow
Page358
WDTOUT
32-state
is output when an overflow occurs, as shown in
Write of a clear code
C
= fsys = 10 MHz,)
WDTOUT
INTWDT
).
SYS
interrupt can be
0
that the clock
TMPM330
16
, 2
18
, 2
SYS
20
,
.