TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 453

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

SECBIT
0x4004_0500
(Note) This register is initialized only by power-on reset.
(Note 1) This command must be issued in the ready state. Issuing the command in the
(Note 2) The FLCS bits [21:20] of TMPM330FWFG have no function. They are read as
(Note 3) The value varies depending on protection applied.
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
Function
Function
Function
Function
busy state may disable both correct command transmission and further
command input. To exit from the condition, execute system reset. System reset
requires at least 0.5 microseconds regardless of the system clock frequency.
In this condition, it takes approx. 2 ms to enable reading after reset.
"0".
31
23
15
7
-
-
-
-
Table 19-3 Security bit register
Under development
30
22
14
6
-
-
-
-
Page441
29
21
13
5
-
-
-
-
“0” i s read
28
20
12
4
R
-
-
-
0
-
“0” i s read
“0” i s read
“0” i s read
R
R
R
0
0
0
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
-
25
17
9
1
-
-
-
-
TMPM330
1:enabled
0:disabled
Security
bits
SECBIT
R/W
24
16
8
0
1
-
-
-