TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 51

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

X1
X2
XT1
XT2
Starts oscillation
Starts oscillation
fperiph
fsys
after reset.
OSCCR1
OSCCR1
after reset
High-speed
oscillator
Low-speed
oscillator
fs
<XTEN>
<XEN>
(Note)
OSCCR0<WUEON>
OSCCR0<WUPT2:0>
Warp-up timer
The input clocks to selector shown with an arrow are set as default after reset.
1/2 1/4 1/8 1/16 1/32
fs
fosc
OSCCR0
<PLLON>
Stops after releasing reset
<WUPSEL>
PLL
OSCCR0
<PLLSEL>
PLLSEL
fpll = fosc × 4
Fig.7-1 Clock Block Diagram
Under development
<PRCK2:0>
fc
SYSCR1
φT0
1/2 1/4 1/8
Page39
1/2
<SCOSEL1:0>
SYSCR2
<GEAR2:0>
SYSCR0
SYSCR1 <FPSEL>
fgear
<SYSCK>
CKSEL
SCOUT
[Peripheral I/O,
prescaler input]
[AHB-Bus I/O]
[IO-Bus I/O]
[RTC]
[CEC, RMC]
TMRB, SIO
CPU, ROM, RAM,
BOOT ROM
TMRB, WDT, RTC,SIO,
SBI, CEC, RMC,
ADC, PORT,
Prescaler input
Sampling clock
fperiph
(To peripheral I/O)
fsys
fs
ADC
clock
ADCLK
conversion
TMPM330