TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 185

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

The block diagram of this mode is shown below.
X; Don’t care −; no change
TB0RG0-WR
TB0EN
TB0RUN
TB0RG0
TB0RG1
TB0CR
TB0FFCR
TB0MOD
PICR
PIFR1
TB0RUN
TB0IN0
φT16
TB0CR<TB0WBF>
φT1
φT4
Each register in the 16-bit PPG output mode must be programmed as listed below.
←
← X
←
←
←
←
←
← X
←
←
←
←
Selector
Selector
7
1
1
0
−
−
*
*
*
*
*
－
X
X
X
6
0
0
−
Fig. 10-4 Block Diagram of 16-bit PPG Mode
*
*
*
*
*
X
X
X
5
0
1
−
−
*
*
*
*
*
X
X
4
0
0
0
−
−
*
*
*
*
*
16-bit comparator
Register buffer 0
(** = 01, 10, 11)
Under development
3
X
X
0
1
0
−
−
*
*
*
*
*
TB0RG0
X
1
2
0
0
1
1
−
−
*
*
*
*
X
X
1
X
0
1
−
−
*
*
*
*
*
Page173
16-bit up-counter UC0
X
0
0
0
0
1
1
1
*
*
*
*
*
Match
Internal data bus
Starts the TMRB0 module.
Stops the TMRB0 module.
Specifies a duty. (16 bits *32-bits for register)
Specifies a cycle. (16 bits *32-bits for register)
Enables the TB0RG0 double buffering.
(Changes the duty/cycle when the INTTB0 interrupt is
generated)
Specifies to trigger TB0FF0 to reverse
when a match with TB0RG0 or TB0RG1 is detected,
and sets the initial value of TB0FF0 to "0."
Designates the prescaler output clock as the input clock,
and disables the capture function.
Assigns PI0 to TB0OUT
Starts TMRB0
TB0RUN<TB0RUN>
16-bit comparator
Register buffer 1
TB0RG1
Clear
TB0OUT (PPG output)
(TB0FF0)
F/F
TMPM330