TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 336

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

14 Remote control signal preprocessor (RMC)
14.3.1.4 Enabling Reception
14.3.1.5 Reception
RMCRCR3 and RMCRCR4 registers, RMC is ready for reception. Detecting a leader initiates
reception.
interrupt is generated if the RMCRCR2 <RMCLIEN> bit is set. When the interrupt is generated, the
RMCRSTAT <RMCRLIF> bit is set.
RMCRBUF1, RMCRBUF 2 and RMCRBUF 3 registers up to 72bit. By setting “1” to the RMCRCR2
<RMCEDIEN> bit, a remote control signal input falling edge interrupt can be generated in each falling
edge of the data bit. When the interrupt is generated, the RMCRSTAT <RMCEDIF> bit is set.
an interrupt.
Register.
reception without detecting a leader.
data is overwritten by the next one.
(Note)
By enabling the RMCREN <RMCREN> bit after configuring the RMCRCR1, RMCRCR2,
Detecting a leader sets the RMCRSTAT <RMCRLDR> bit. Simultaneously, a leader detection
Next to the leader detection, each data bit is determined as 0 or 1. The results are stored in the
Detecting the maximum data bit cycle or the excess low width completes reception and generates
To check the status of RMC after reception is completed, read the Remote Control Receive Status
On completion of reception, RMC is waiting for the next leader.
By setting RMC to receive a signal without a leader, RMC recognizes the received is data and starts
If the next data reception is completed before reading the preceding received data, the preceding
Changing the configurations of the RMCRCR1, RMCRCR2, RMCRCR3 and
RMCRCR4 registers during reception may harm their proper operation. Be careful
if you change them during reception.
Under development
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TMPM330