TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 294

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
13.2.9
(Note)
Receive Control Register 3 [CECRCR3]
bit Symbol
Read/Write
After reset
Read/Write
Read/Write
bit Symbol
After reset
bit Symbol
After reset
Function
Function
Function
Changing the configurations during transmission or reception may harm its proper
operation. Before the change, configure the <CECREN> bits to disable the reception
and read the <CECREN> bit to ensure that the operation is stopped.
“0” is
read.
“0” is
read.
23
15
―
―
R
R
7
0
0
The latest rising timing of logical “0”
determined as proper waveform.
000: 1.7ms
001: 1.7ms+1cycle
010: 1.7ms+2cycles
011: 1.7ms+3cycles
100: 1.7ms+4cycles
101: 1.7ms+5cycles
110: 1.7ms+6cycles
111: 1.7ms+7cycles
The latest rising timing of logical “1”
determined as proper waveform.
000: 0.8ms
001: 0.8ms+1cycle
010: 0.8ms+2cycles
011: 0.8ms+3cycles
100: 0.8ms+4cycles
101: 0.8ms+5cycles
110: 0.8ms+6cycles
111: 0.8ms+7cycles
WAV32
WAV12
CEC
CEC
22
14
6
Under development
Page282
WAV31
WAV11
CEC
CEC
R/W
R/W
21
13
5
0
0
“0” is read.
WAV30
WAV10
CEC
CEC
20
12
―
4
R
0
“0” is
read.
“0” is
read.
19
11
―
―
R
R
3
0
0
The fastest rising timing of logical
“0” determined as proper
waveform.
000: 1.3ms
001: 1.3ms-1cycle
010: 1.3ms-2cycles
011: 1.3ms-3cycles
100: 1.3ms-4cycles
101: 1.3ms-5cycles
110: 1.3ms-6cycles
111: 1.3ms-7cycles
The fastest rising timing of logical
“1” determined as proper
waveform.
000: 0.4ms
001: 0.4ms-1cycle
010: 0.4ms-2cycles
111: 0.4ms-3cycles
100: 0.4ms-4cycles
101: 0.4ms-5cycles
110: 0.4ms-6cycles
111: 0.4ms-7cycles
WAV22
WAV02
CEC
CEC
18
10
2
WAV21
WAV01
CEC
CEC
R/W
R/W
17
9
1
0
0
TMPM330
Waveform
error
detection
1:
Enabled
0:
Disabled
WAVEN
WAV20
WAV00
CEC
CEC
CEC
R/W
16
8
0
0