TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 418

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

18 Flash Memory Operation
8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the
9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate
10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the
11. The 26th byte, transmitted from the target board to the controller, is an acknowledge
response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive
error in the 5th to 17th bytes. If there was a receive error, the boot program sends back
18H (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte)
again. In this case, the upper four bits of the acknowledge response are the same as
those of the previously issued command (i.e., all 1s). When the SIO0 is configured for
I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data
integrity. Adding the series of the 5th to 16th bytes must result in 00H (with the carry
dropped). If it is not 00H, one or more bytes of data has been corrupted. In case of a
checksum error, the RAM Transfer routine sends back 11H to the controller and returns
to the state in which it waits for a command (i.e., the 3rd byte) again.
Finally, the RAM Transfer routine examines the result of the password verification. The
following two cases are treated as a password error. In these cases, the RAM Transfer
routine sends back 11H (bit 0) to the controller and returns to the state in which it waits
for a command (i.e., the 3rd byte) again.
•
password in the flash memory are the same value other than FFH.
Not the entire password bytes transmitted from the controller matched those contained
in the flash memory.
When all the above verification has been successful, the RAM Transfer routine returns
a normal acknowledge response (10H) to the controller.
start address of the RAM region where subsequent data (e.g., a flash programming
routine) should be stored. The 19th byte corresponds to bits 31–24 of the address and
the 22nd byte corresponds to bits 7–0 of the address.
the number of bytes that will be transferred from the controller to be stored in the RAM.
The 23rd byte corresponds to bits 15–8 of the number of bytes to be transferred, and
the 24th byte corresponds to bits 7–0 of the number of bytes.
checksum value, add all these bytes together, drop the carries and take the two’s
complement of the total sum. Transmit this checksum value from the controller to the
target board. The checksum calculation is described in details in a later section
“Checksum Calculation”.
response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a
receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer
routine sends back 18H and returns to the command wait state (i.e., the 3rd byte) again.
In this case, the upper four bits of the acknowledge response are the same as those of
the previously issued command (i.e., all 1s). When the SIO0 is configured for I/O
Interface mode, the RAM Transfer routine does not check for a receive error.
Irrespective of the result of the password comparison, all the 12 bytes of a
Under development
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TMPM330