TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 366

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

15 Analog/Digital Converter
15.5 High-priority Conversion Mode
15.6 A/D Monitor Function
15.7 Storing and Reading A/D Conversion Results
By interrupting ongoing normal A/D conversion, top-priority A/D conversion can be
performed. Top-priority A/D conversion can be software activated by setting
ADMOD2<HPADCE> to "1" or it can be activated using the HW resource by setting
ADMOD3<7:6> to an appropriate setting.
activated during normal A/D conversion, ongoing normal A/D conversion is interrupted,
and single conversion is performed for a channel designated by ADMOD2<3:0>. The
result of single conversion is stored in ADREGSP, and the top-priority A/D conversion
interrupt is generated. After top-priority A/D conversion is completed, normal A/D
conversion is resumed; the status of normal A/D conversion immediately before being
interrupted is maintained. Top-priority A/D conversion activated while top-priority A/D
conversion is under way is ignored.
For example, if channel repeat conversion is activated for channels AN0 through AN8
and if <HPADCE> is set to "1" during AN3 conversion, AN3 conversion is suspended,
and conversion is performed for a channel designated by <HPADC3:0>. After the result
of conversion is stored in ADREGSP, channel repeat conversion is resumed, starting
from AN3.
If ADCMPx<ADOBSVx> is set to "1," the A/D monitor function is enabled. If the value of
the conversion result storage register specified by REGS<3:0> becomes larger or
smaller ("larger" or "smaller" to be designated by ADOBIC) than the value of a
comparison register, the A/D monitor function interrupt is generated. This comparison
operation is performed each time a result is stored in a corresponding conversion result
storage register, and the interrupt is generated if the conditions are met. Because storage
registers assigned to perform the A/D monitor function are usually not read by software,
overrun flag <OVRn> is always set and the conversion result storage flag <ADRnRF> is
also set. To use the A/D monitor function, therefore, a flag of a corresponding conversion
result storage register must not be used.
A/D conversion results are stored in upper and lower A/D conversion result registers for
normal A/D conversion (ADREG08H/L through ADRG7FH/L).
In fixed channel repeat conversion mode, A/D conversion results are sequentially stored
in ADREG08H/L through ADREG7FH/L. If <ITM1:0> is so set as to generate the interrupt
each time one A/D conversion is completed, conversion results are stored only in
ADREG08H/L. If <ITM1:0> is so set as to generate the interrupt each time four A/D
conversions are completed, conversion results are sequentially stored in ADREG08H/L
through ADREG3BH/L.
Table 15-2 shows analog input channels and related A/D conversion result registers.
Under development
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If top-priority A/D conversion has been
TMPM330