TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 417

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

3. The 3rd byte transmitted from the controller to the target board is a command. The
4. The 4th byte, transmitted from the target board to the controller, is an acknowledge
5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte
6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To
7. The 18th byte, transmitted from the target board to the controller, is an acknowledge
code for the RAM Transfer command is 10H.
response to the 3rd byte. Before sending back the acknowledge response, the boot
program checks for a receive error. If there was a receive error, the boot program
transmits x8H (bit 3) and returns to the state in which it waits for a command (the third
byte) again. In this case, the upper four bits of the acknowledge response are
undefined - they hold the same values as the upper four bits of the previously issued
command. When the SIO0 is configured for I/O Interface mode, the boot program does
not check for a receive error.
If the 3rd byte is equal to any of the command codes listed in Table 18-4, the boot
program echoes it back to the controller. When the RAM Transfer command was
received, the boot program echoes back a value of 10H and then branches to the RAM
Transfer routine. Once this branch is taken, password verification is done. Password
verification is detailed in a later section “Password”. If the 3rd byte is not a valid
command, the boot program sends back x1H (bit 0) to the controller and returns to the
state in which it waits for a command (the third byte) again. In this case, the upper four
bits of the acknowledge response are undefined - they hold the same values as the
upper four bits of the previously issued command.
password. Each byte is compared to the contents of following addresses in the flash
memory. The verification is started with the 5
designated area. If the password verification fails, the RAM Transfer routine sets the
password error flag.
calculate the checksum value for the 12-byte password, add the 12 bytes together,
drop the carries and take the two’s complement of the total sum. Transmit this
checksum value from the controller to the target board. The checksum calculation is
described in details in a later section “Checksum Calculation”.
SC0BUF. Then, the SIO0 waits for the SCLK0 signal to come from the controller.
Following the transmission of the 1st byte, the controller should send the SCLK clock
to the target board after a certain idle time (several microseconds). This must be done
at 1/16 the desire baud rate. If the 2nd byte, which is from the target board to the
controller, is 30H, then the controller should take it as a go-ahead. The controller must
then deliver the 3rd byte to the target board at a rate equal to the desired baud rate.
The boot program sets the RXE bit in the SC0MOD register to enable reception before
loading the SIO transmit buffer with 30H.
TMPM330FWFG
TMPM330FDFG
TMPM330FYFG
Product name
Under development
0x3F87_FF04 – 0x3F87_FF0F
0x3F81_FF04 – 0x3F81_FF0F
Page405
Area
th
byte and the smallest address in the
TMPM330