TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 227

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

11.4.11 RX FIFO status register
11.4.12 TX FIFO status register
SC0RST
SC0TST
<ROR>:
<RLVL2:0>:
(Note)
<TUR>:
<TLVL2:0>:
(Note)
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
The <ROR> bit is cleared to “0” when receive data is read from the SC0BUF
register.
The <TUR> bit is cleared to “0” when transmit data is written to the SC0BUF
register.
Function
Function
Flags for RX FIFO overrun. When the overrun occurs, these bits are set to “1”
Flags for TX FIFO underrun. When the underrun occurs, these bits are set to “1”
note).
Shows the fill level of TX FIFO.
Shows the fill level of RX FIFO.
RX FIFO
Overrun
1:
Generate
d
TX FIFO
Under run
1:Generat
ed
Cleared
by writing
FIFO
ROR
TUR
7
R
7
R
0
1
“0” is read.
“0” is read.
Under development
6
6
Page215
5
5
R
R
0
0
4
4
3
3
000:Empty
001:1Byte
010:2Byte
011:3Byte
100:4Byte
000:Empty
001:1Byte
010:2Byte
011:3Byte
100:4Byte
Status of RX FIFO fill level
Status of TX FIFO fill level
RLVL2
TLVL2
2
2
0
0
RLVL1
TLVL1
１
1
R
R
0
0
(see note).
TMPM330
RLVL0
TLVL0
0
0
0
0
(see