TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 184
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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10 16-bit Timer/Event Counters (TMRBs)
10.6.3
Match with B0RG0
Match with B0RG1
TB0OUT pin
16-bit Programmable Square Wave Output Mode (PPG)
(INTTB0 interrupt)
(INTTB1 interrupt)
Match with TB0RG0
Match with TB0RG1
TB0RG0
(compare value)
Register buffer
Square waves with any frequency and any duty (programmable square waves) can be
output. The output pulse can be either low-active or high-active.
Programmable square waves can be output from the TB0OUT pin by triggering the timer
flip-flop (TB0FF) to reverse when the set value of the up-counter (UCO) matches the set
values of the timer registers (TB0RG0 and TB0RG1). Note that the set values of TB0RG0
and TB0RG1 must satisfy the following requirement:
In this mode, by enabling the double buffering of TB0RG0, the value of register buffer 0 is
shifted into TB0RG0 when the set value of the up-counter matches the set value of
TB0RG1. This facilitates handling of small duties.
Fig. 10-2 Example of Output of Programmable Square Wave (PPG)
(Set value of TB0RG0) < (Set value of TB0RG1)
Up-counter = Q
Fig. 10-3 Register Buffer Operation
Under development
1
Q
1
Page172
Q
2
Trigger to shift to TB0RG1
Up-counter = Q
Write TB0RG0
Q
2
2
Q
3
TMPM330
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