TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 257

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12.5.4
12.5.5
Internal SCL output (master B)
Internal SCL output (master A)
Slave Addressing and Address Recognition Mode
Configuring the SBI as a Master or a Slave
SCL line
Clock Synchronization
The I
master that pulls its clock line to the “L” level overrides other masters producing the “H” level
on their clock lines. This must be detected and responded by the masters producing the “H”
level.
Clock synchronization assures correct data transfer on a bus that has two or more master.
For example, the clock synchronization procedure for a bus with two masters is shown
below.
line to the “L” level. Master B detects this transition, resets its “H” level period counter, and
pulls its internal SCL output level to the “L” level.
Master A completes counting of its “L” level period at the point b, and brings its internal SCL
output to the “H” level. However, Master B still keeps the SCL bus line at the “L” level, and
Master A stops counting of its “H” level period counting. After Master A detects that Master
B brings its internal SCL output to the “H” level and brings the SCL bus line to the “H” level at
the point c, it starts counting of its “H” level period.
This way, the clock on the bus is determined by the master with the shortest “H” level period
and the master with the longest “L” level period among those connected to the bus.
When the SBI is configured to operate as a slave device, the slave address <SA6:0> and
<ALS> must be set at SBIxI2CAR. Setting <ALS> to “0” selects the address recognition
mode.
hardware when it detects the stop condition on the bus or the arbitration lost.
At the point a, Master A pulls its internal SCL output to the “L” level, bringing the SCL bus
Setting SBIxCR2<MST> to “1” configures the SBI to operate as a master device.
Setting <MST> to “0” configures the SBI as a slave device. <MST> is cleared to “0” by the
2
C bus is driven by using the wired-AND connection due to its pin structure. The first
Fig. 12-9 Example of Clock Synchronization
Under development
a
Reset high-level
period counting
Page245
Wait for high-level
period counting
b
c
Start high-level period counting
TMPM330