TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 9
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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14
15
13.3
14.1
14.2
14.3
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.2.9
13.2.10
13.2.11
13.2.12
13.2.13
13.2.14
13.3.1
13.3.2
13.3.3
14.1.1
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.2.9
14.2.10
14.2.11
14.3.1
Remote control signal preprocessor (RMC) ............................................................. 309
Analog/Digital Converter............................................................................................. 333
Operations ................................................................................................................ 290
Basic operation ........................................................................................................ 309
Registers ................................................................................................................... 310
Operation Description ............................................................................................. 320
CEC Enable Register [CECEN]........................................................................ 275
Logical Address Register [CECADD] ............................................................. 275
Software Reset Register [CECRESET] ........................................................... 276
Receive Enable Register [CECREN] ............................................................... 276
Receive Buffer Register [CECRBUF].............................................................. 277
Receive Control Register 1 [CECRCR1]......................................................... 278
Receive Control Register 2 [CECRCR2]......................................................... 280
Receive Control Register 3 [CECRCR3]......................................................... 282
Reception .......................................................................................................... 290
Transmission .................................................................................................... 301
Software Reset.................................................................................................. 307
Reception of Remote Control Signal.............................................................. 309
Register Map ..................................................................................................... 310
Remote Control Enable Register [RMCEN].................................................... 311
Remote Control Receive Enable Register [RMCREN] .................................. 311
Remote Control Receive Data Buffer Register 1 [RMCRBUF1] ................... 312
Remote Control Receive Data Buffer Register 2 [RMCRBUF2] ................... 313
Remote Control Receive Data Buffer Register 3 [RMCRBUF3] ................... 313
Remote Control Receive Control Register 1 [RMCRCR1] ............................ 314
Remote Control Receive Control Register 2 [RMCRCR2] ............................ 316
Remote Control Receive Control Register 3 [RMCRCR3] ............................ 317
Reception of Remote Control Signal.............................................................. 320
Transmit Enable Register [CECTEN] .......................................................... 284
Transmit Buffer Register [CECTBUF] ......................................................... 285
Transmit Control Register [CECTCR] ......................................................... 286
Receive Interrupt Status Register [CECRSTAT] ........................................ 288
Transmit Interrupt Status Register [CECTSTAT] ....................................... 289
Remote Control Receive Control Register 4 [RMCRCR4] ........................ 318
Remote Control Receive Status Register [RMCRSTAT]............................ 319
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