TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 374

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

16 Watchdog Timer (Runaway Detection Timer)
(Note 1) If the watchdog timer is operated when the high-frequency oscillator is idle, the system reset
operation initiated by the watchdog timer becomes erratic due to the unstable oscillation of the
high-frequency oscillator. Therefore, do not operate the watchdog timer when the high-frequency
oscillator is idle.
(Note 2) The counter of the watchdog timer stops at the debug mode.
16.4 Control Register
The watchdog timer generates the
the WDMOD <WDTP1, 0> register and outputs a signal at low level from the output pin of the
watchdog timer (
watchdog timer must be cleared to "0" using software (instruction). If the CPU malfunctions
(runaways) due to noise or other disturbances and cannot execute the instruction to clear the binary
counter, the binary counter overflows and the non-maskable interrupt is generated by the
interrupt. The CPU is able to recognize the occurrence of a malfunction (runaway) by identifying the
non-maskable interrupt and to restore the faulty condition to normal by using a malfunction (runaway)
countermeasure program. Additionally, it is possible to resolve the problem of a malfunction
(runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices.
The watchdog timer begins operation immediately after a reset is cleared.
"L"), it continues counting. In IDLE mode, its operation depends on the WDMOD <I2WDT> setting.
Before putting it in IDLE mode, WDMOD <I2WDT> must be set to an appropriate setting, as required.
(Note)
In STOP mode, the watchdog timer is reset and in an idle state. When the bus is released (
(Note)
Example:
The TMPM330 does not include a watchdog timer out pin (
Releasing bus is disabled since no external bus feature is available on the
TMPM330.
1. To clear the binary counter
2. To set the detection time of the watchdog timer to 2
3. To disable the watchdog timer.
WDMOD ( 0 ( ( ( ( ( ( (
WDMOD ← 1 0 1
WDCR ( 1 0 1 1 0 0 0 1
WDCR
WDTOUT
← 0 1 0 0 1 1 1 0
). Before generating the
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1
− − − − (
Under development
INTWDT
Page362
0
interrupt after a lapse of the detection time specified by
Writes the clear code
Clears WDTE to "0"
Writes the disable code (B1H)
INTWDT
interrupt, the binary counter for the
18
/f
SYS.
(4EH)
WDTOUT
).
TMPM330
BUSAK
INTWDT
=