TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 277
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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12.7.1
SCK pin output
SO pin output
Write the
transmit data
Serial Clock
Internal clocks
External clock (<SCK2:0> = “111”)
Fig. 12-25 Maximum Transfer Frequency of External Clock Input
Clock source
In the internal clock mode, one of the seven frequencies can be selected as a serial
clock, which is output to the outside through the SCK pin. At the beginning of a
transfer, the SCK pin output becomes the “H” level.
If the program cannot keep up with this serial clock rate in writing the transmit data or
reading the received data, the SBI automatically enters a wait period. During this
period, the serial clock is stopped automatically and the next shift operation is
suspended until the processing is completed.
The SBI uses an external clock supplied from the outside to the SCK pin as a serial
clock. For proper shift operations, the serial clock at the “H” and “L” levels must have
the pulse widths as shown below.
Internal or external clocks can be selected by programming SBIxCR1 <SCK2:0>.
SCK pin
a
a
1
0
t
SCKL
a
2
, t
1
SCKH
Fig. 12-24 Automatic Wait
a
t
SCK
2
3
a
> 4/fsys
L
Under development
5
t
SCK
a
Page265
7
H
6
a
8
7
Automatic wait
b
b
1
0
b
1
2
c
b
4
b
6
5
b
7
6
b
8
7
c
1
0
c
2
1
TMPM330
c
3
2
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