TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 7

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

12
11.4
11.5
12.1
11.3.7
11.3.8
11.3.9
11.3.10
11.3.11
11.3.12
11.3.13
11.3.14
11.3.15
11.3.16
11.3.17
11.3.18
11.3.19
11.3.20
11.3.21
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
register 2(SC0BRADD) .................................................................................................... 210
11.4.8
11.4.9
11.4.10
11.4.11
11.4.12
11.5.1
11.5.2
11.5.3
11.5.4
Serial Bus Interface (SBI) ............................................................................................ 231
Register Description (Only for Channel 0) ............................................................ 205
Operation in Each Mode .......................................................................................... 216
Configuration............................................................................................................ 232
Receive FIFO Buffer ......................................................................................... 194
Receive FIFO Operation................................................................................... 194
Transmit Counter.............................................................................................. 196
Enable register.................................................................................................. 205
Buffer register ................................................................................................... 205
Control register................................................................................................. 206
Mode control register 0.................................................................................... 207
Mode control register 1.................................................................................... 208
Mode control register 2.................................................................................... 209
Baud rate generator control register(SC0BRCR) Baud rate generator control
FIFO configuration register ............................................................................. 212
RX FIFO configuration register ....................................................................... 213
Mode 0 (I/O interface mode) ............................................................................ 216
Mode 1 (7-bit UART Mode)............................................................................... 226
Mode 2 (8-bit UART Mode)............................................................................... 227
Mode 3 (9-bit UART) ....................................................................................... 228
Transmit Control Unit ................................................................................... 196
Transmit Buffer ............................................................................................. 198
Transmit FIFO Buffer .................................................................................... 199
Transmit FIFO Operation.............................................................................. 199
Parity Control Circuit.................................................................................... 201
Error Flag....................................................................................................... 201
Direction of Data Transfer............................................................................ 202
Stop Bit Length ............................................................................................. 202
Status Flag..................................................................................................... 202
Configurations of Transmit/Receive Buffer ............................................... 203
Software reset ............................................................................................... 203
Signal Generation Timing ............................................................................ 204
TX FIFO configuration register.................................................................... 214
RX FIFO status register ................................................................................ 215
TX FIFO status register ................................................................................ 215
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