TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 364

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TMPM330FWFG

Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Datasheets

Specifications of TMPM330FWFG

Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM330FWFG
Manufacturer:
Toshiba
Quantity:
10 000
15 Analog/Digital Converter
3.
4.
Fixed channel repeat conversion mode
If ADMOD0<REPEAT,SCAN> is set to "10," A/D conversion is performed in fixed channel
repeat conversion mode.
In this mode, A/D conversion is performed repeatedly for one channel selected. After A/D
conversion is completed, ADMOD <EOCF> is set to "1." ADMOD0 <ADBF> is not
cleared to "0." It remains at "1." The timing with which the interrupt request INTAD is
generated can be selected by setting ADMOD0 <ITM1:0> to an appropriate setting.
<EOCF> is set with the same timing as this interrupt INTAD is generated.
<EOCF> is cleared to "0" upon read.
With <ITM1:0> set to "00," an interrupt request is generated each time one A/D
conversion is completed. In this case, the conversion results are always stored in the
storage register ADREG08. After the conversion result is stored, EOCF changes to "1."
With <ITM1:0> set to "01," an interrupt request is generated each time four A/D
conversion are completed. In this case, the conversion results are sequentially stored in
storage registers ADREG08 through ADREG3B. After the conversion results are stored
in ADREG3B, <EOCF> is set to "1," and the storage of subsequent conversion results
starts from ADREG08. <EOCF> is cleared to "0" upon read.
<EOCF> is cleared to "0" upon read.
Channel scan repeat conversion mode
If ADMOD0 <REPEAT, SCAN> is set to "11," A/D conversion is performed in the channel
scan repeat conversion mode.
In this mode, A/D conversion is performed repeatedly for a scan channel selected. Each
time one A/D scan conversion is completed, ADMOD0 <EOCF> is set to "1," and the
interrupt request INTAD is generated. ADMOD0 <ADBF> is not cleared to "0." It remains
at "1." <EOCF> is cleared to "0" upon read.
To stop the A/D conversion operation in the repeat conversion mode (modes described in
3. and 4. above), write "0" to ADMOD0 <REPEAT>. When ongoing A/D conversion is
completed, the repeat conversion mode terminates, and ADMOD0 <ADBF> is set to "0."
Before switching from one mode to standby mode (such standby modes as IDLE, STOP,
etc.), check that A/D conversion is not being executed. If A/D conversion is under way,
you must stop it or wait until it is completed.
The ADMOD0<REPEAT, SCAN> setting has no relevance to the top-priority A/D
conversion operations or preparations. As activation requirements are met, A/D
conversion is performed only once for a channel designated by ADMOD2<HPADCH3:0>.
After the A/D conversion is completed, the top-priority A/D conversion completion
interrupt is generated, ADMOD2<EOCFHP> is set to "1," and <ADBFHP> returns to "0."
The EOCFHP Flag is cleared upon read.
With <ITM1:0> set to "10," an interrupt request is generated each time eight A/D
conversions are completed. In this case, the conversion results are sequentially stored
in storage registers ADREG08 through ADREG7F. After the conversion results are
stored in ADREG7F, <EOCF> is set to "1," and the storage of subsequent conversion
results starts from ADREG08.
(2)Top-priority A/D conversion
Top-priority A/D conversion is performed only in fixed channel single conversion mode.
Under development
Page352
TMPM330

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