TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 314
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Company
Part Number
Manufacturer
Quantity
Price
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13 Consumer Electronics Control (CEC)
13.3.2.2 Preconfiguration
(1)
(2)
(3)
to 16 bit cycles.
signal stays high for the specified number of bit cycles, transmission starts.
<CECSTRS> <CECSPRD> <CECDTRS> <CECDPRD> bits, the timing can be specified between
the defined fastest rising/cycle timing and the reference value.
logical “0” and logical “1”.
transmit buffer <CECTBUF> are required.
response during an ACK cycle results in an error. If not, “1” response during an ACK cycle results in
an error.
(Reference)
Before transmitting data, transmission settings to the Transmit Control Register CECTCR>and the
Specify the bus free wait time in the CECTCR<CECFREE> bits. It can be specified in a range of 1
Counting of the bus free wait time begins one bit cycle after the falling edge of the final bit. If the
Set the CECTCR <CECBRD> bit when transmitting a broadcast message. If this bit is set, “0”
Both start bit and data bit are capable of adjusting the rising timing and cycle. With the CECTCR
The following figures show how the waveforms differ according to the configurations of the start bit,
Bus Free Wait Time
Transmitting Broadcast Message
Adjusting Transmission Waveform
The configuration of <CECDTRS> is applied for waveform of an ACK response
during reception. The ACK response and the logical “0” output show the same
waveform.
Final bit
Under development
Bus free wait time
Page302
Beginning of
transmission
TMPM330
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