TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 437

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(4) Commands
1) Automatic Page Programming
Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell
cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is
necessary to perform an erase operation.
The automatic page programming function of this device writes data of each page. The
TMPM330FDFG/ TMPM330FYFG contain 128 words and the TMPM330FWFG contains 64
words in a page. A 128 word block is defined by a same [31:9] address and it starts from the
address [8:0] = 0 and ends at the address [8:0] = 0x1FF. A 64 word block is defined by a
same [31:8] address and it starts from the address [7:0] = 0 and ends at the address [7:0] =
0xFF. This programming unit is hereafter referred to as a "page."
control by the CPU is required. The state of automatic page programming (whether it is in
writing operation or not) can be checked by the FLCS [0] <RDY/BSY> register.
Also, any new command sequence is not accepted while it is in the automatic page
programming mode. If it is desired to interrupt the automatic page programming, use the
hardware reset function. If the operation is stopped by a hardware reset operation, it is
necessary to once erase the page and then perform the automatic page programming
again because writing to the page has not been normally terminated.
The automatic page programming operation is allowed only once for a page already erased.
No programming can be performed twice or more times irrespective of the data cell value
whether it is "1" or "0." Note that rewriting to a page that has been once written requires
execution of the automatic block erase or automatic chip erase command before executing
the automatic page programming command again. Note that an attempt to rewrite a page
two or more times without erasing the content can cause damages to the device.
No automatic verify operation is performed internally to the device. So, be sure to read the
data programmed to confirm that it has been correctly written.
The automatic page programming operation starts when the third bus write cycle of the
command cycle is completed. On and after the fifth bus write cycle, data will be written
sequentially starting from the next address of the address specified in the fourth bus write
cycle (in the fourth bus write cycle, the page top address will be command written) (32 bits
of data is input at a time). Be sure to use the 32-bit data transfer command in writing
commands on and after the fourth bus cycle. In this, any 32-bit data transfer commands
shall not be placed across word boundary. On and after the fifth bus write cycle, data is
command written to the same page area. Even if it is desired to write the page only partially,
it is required to perform the automatic page programming for the entire page. In this case,
the address input for the fourth bus write cycle shall be set to the top address of the page.
Be sure to perform command write operation with the input data set to "1" for the data cells
not to be set to "0." For example, if the top address of a page is not to be written, set the
input data of the fourth bus write cycle to 0xFFFFFFFF to command write the data.
Once the fourth bus cycle is executed, it is in the automatic programming operation. This
condition can be checked by monitoring the register bit FLCS [0] <RDY/BSY> (See Table
18-15). Any new command sequence is not accepted while it is in automatic page
programming mode. If it is desired to stop operation, use the hardware reset function. Be
Writing to data cells is automatically performed by an internal sequencer and no external
Under development
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TMPM330