TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 295
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
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<CECWAV3 2:0>:
<CECWAV2 2:0>:
<CECWAV1 2:0>:
<CECWAV0 2:0>:
<CECWAVEN>:
This setting is enabled when the <CECWAVEN> bit is set to “1”.
Detects a received waveform does not identical to the one defined and generates
This setting is enabled when the <CECWAVEN> bit is set to “1”.
By setting these bits, an error is detected if rising edge of the received waveform
comes faster than logical “0” and later than that of proper logical “1”.
Enables to set <CECWAV1> for each sampling clock cycle between the ranges of 0
to 7 cycles from defined maximum tolerance (0.8 ms) of logical “1” waveform.
Enables to set <CECWAV2> for each sampling clock cycle between the ranges of 0
to -7 cycles from defined minimum tolerance (1.3 ms) of logical “0” waveform.
The received waveform is considered to be an error if a rising edge is detected
between the values specified in <CECWAV2> and <CECWAV1>.
By setting these bits, an error is detected if rising edge of the received waveform
comes faster than that of proper logical “1”. Enables to set <CECWAV0> for each
sampling clock cycle between the ranges of 0 to -7 cycles from defined minimum
tolerance (0.4 ms).
The received waveform is considered to be an error if a rising edge is not detected
from a start point of the bit to the value specified in <CECWAV0>.
waveform error interrupt.
If enabled, an error is detected according to the setting of <CECWAV0>
<CECWAV1> <CECWAV2> <CECWAV3>.
This setting is enabled when the <CECWAVEN> bit is set to “1”.
By setting these bits, an error is detected if rising edge of the received waveform
comes later than that of proper logical “0”. Enables to set it for each sampling clock
cycle between the ranges of 0 to 7 cycles from defined maximum tolerance (1.7
ms). The received waveform is considered to be an error if a rising edge is not
detected from the start point of the bit to the value specified in <CECWAV3>.
Under development
Page283
TMPM330
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