TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 446

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

Address
[TMPM330FDFG/ FYFG/ FWFG]
Normal
commands
ID
-READ
[TMPM330FDFG/ TMPM330FYFG]
Block erase
Auto page
programming
Protection bit
programming
Protection bit
erase
[TMPM330FWFG only]
Block erase
Auto
page
program
ming
Protection bit
programming
Protection bit
erase
18 Flash Memory Operation
(7) Address bit configuration for bus write cycles
(Note 1)
(Note 3)
(Note 2)
PBA: Protection bit address
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
PA: Program page address (Set the fourth bus write cycle address for page programming operation)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure)
Flash area
Flash area
Flash area
Flash area
Flash area
Flash area
[31:19]
Addr
Table 18-17 "Flash Memory Access from the Internal CPU" can also be used.
Address setting can be performed according to the "Normal bus write cycle address
configuration" from the first bus cycle.
"0" is recommended" can be changed as necessary.
Block selection (Table 18-19)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
BA: Block address (Set the sixth bus write cycle address for block erase operation)
Table 18-18 Address Bit Configuration for Bus Write Cycles
IA: ID address (Set the fourth bus write cycle address for ID-Read operation)
Protection bit selection
Addr
(Table 18-21)
(Table 18-20)
(Table 18-21)
Protection bit
Protection bit
Protection bit
[18]
“0” is recommended.
“0” is recommended.
Block selection
(Table 18-19)
selection
selection
selection
(Table 18-20)
Addr
[17]
Normal bus write cycle address configuration
(
Addr
[16]
Set the seventh bus write cycle address for protection bit programming
Page selection
Addr
Under development
[15]
Page selection
ID address
“0” is recommended.
Page434
Addr
[14]
Fixed to “0”.
Fixed to “0”.
Fixed to “0”.
[13:11]
Addr
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Command
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
Addr[1:0]=“0” (fixed) , Others:0 (recommended)
(Table 18-20)
(Table 18-21)
Addr
Protection bit
Protection bit
[10]
selection
selection
Addr
(Table 18-20)
(Table 18-21)
Protection bit
Protection bit
[9]
selection
selection
Addr
[8]
Others:0 (recommended)
Others:0 (recommended)
Others:0 (recommended)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
Addr[1:0]=“0” (fixed)
(recommended)
(recommended)
(recommended)
(recommended)
Others:0
Others:0
Others:0
Others:0
TMPM330
[7:0]
Addr