TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 312

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13 Consumer Electronics Control (CEC)
13.3.1.10
timeout occurs. Thus, an interrupt is generated in each reception of a byte of data if multiple bytes
are received while interrupts are suspended. “1” is set to the bits of the CECRSTAT register: the
<CECRIEND> bit that indicates the reception completion, and the bits corresponding to the detected
errors. The flags of the suspended interrupts and the reception completion are set to the bits of the
CECRSTAT register.
disabling the bit during reception. The received data is discarded.
(Note 1)
(Note 2)
(Note)
The information that the interrupts are suspended is held until the EOM bit is received or the
Writing “0” to the CECREN <CECREN> bit disables data reception. The reception is stopped upon
Stopping Reception
If the reception is disabled while “0” is sent as a signal of minimum cycle error, the
“0” output is stopped as well.
A minimum cycle error interrupt is generated upon detecting a minimum cycle
error in the next received bit while interrupts are suspended. “0” is output to CEC
for approx. 3.6 ms.
The flags of the suspended interrupts and the minimum cycle error are set to the
bits of the CECRSTAT register.
If an interrupt other than a minimum cycle error interrupt is generated while
interrupts are suspended, CEC continues reception until the ACK response or the
timeout.
All the flags of the detected interrupts are set to the bits of the CECRSTAT register.
Under development
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TMPM330